Mike's PBX Cookbook

UDT E1 T1 clocks

These are built in ld 73, and 60. On Rls 5.0 and above the clocking is a little bit different. Each Media Gateway that has a digital service must have a clock card on it. If the main clock is tied to an E1 then all clocks must be E1 clocks.

Typical Rls 5.0 and above hardware:

Clock Configuration:

Place the UDT/PRI/DTI card (with Clock Controller) close to the MGC, preferably in slot one.
Remember, UDT cards must be configured via a TTY first, depending on the circuit configuration.

Define the clock controller parameters in LD 73:

REQ  chg
TYPE pri2          Either PRI2/DTI2/JDMI/DDB FOR T1
FEAT syti
MGCLK 0 0 1        Superloop, shelf, card of UDT pack with a clock daughter board
PREF 1             Card-slot of the loop providing the Primary Reference (= MGCLK card)
SREF               Secondary reference (if applicable)
MGCLK              Enter next MG, or <enter> to finish

Each Media Gateway (with digital services) requires a clock controller. Print SYTI (or DDB) in LD 73 to list them.

Clock Controller Maintenance:

A clock controller can operate in one of two modes: tracking and non-tracking (free-run).

Tracking: The clock controller will try and lock to a reference PRI's clock (PREF or SREF, LD 73). If the clock reference is stable, the clock controller will "track" it. There are two stages to clock controller tracking: tracking a reference, and locked onto a reference. The clock controllers should be locked to the reference clock. The secondary reference acts as a backup to the primary reference.

Free-run (non-tracking): The clock controller does not refence any source, but provides its own clock to the system, eg, a Master. Free-run is undesirable if the system is intended to be a slave. If both PREF and SREF are lost, the system will revert to Free-run.

Clock controller comands in LD 60:

WARNING Disable the D-channel and clock-controller daughterboards before unseating/replacing a UDT card. Otherwise, the system performs an INIT and this momentarily interrupts call processing.

Status:

A clock controller may track it's primary clock (PCK), or secondary clock (SCLK) reference, or set to free run (FRUN) mode.
If you experience excessive slips after a PRI outage (DTA103 errors), its very likely that the clock controller is either disabled, or has switched to free-run, when it should be tracking. Its good practice to check the clock status after a circuit returns to service.

To find UDT CC daughter board location(s), go to LD 73 and print PRI2 SYTI (system timers):

>LD 73

REQ:  PRT
TYPE: PRI2
FEAT: SYTI
       
MGCLK 0 0 1                Superloop, shelf, and card number of Clock Controller for IPMG
PREF  0 0 1                Primary clock Reference PRI card, usually the PRI on this card
SREF  0 0 2                Secondary clock Reference PRI card, cannot be the same as PREF
 
MGCLK 4 0 1   
PREF  4 0 1
SREF 

CCGD   15                  Clock Controller free run Guard time
CCAR   15                  Clock Controller Audit Rate

To check the status of UDT CC daughter board(s), go to LD 60 and enter SSCK:

>LD 60

.ssck 0 0 
ENBL                       Use 'enl cc l s' to enable the clock controller if necessary
CLOCK ACTIVE 
CLOCK CONTROLLER -  LOCKED TO SLOT 1 
PREF - 1 
SREF - 2
AUTO SWREF CLK - ENBL

.ssck 4 0
ENBL 
CLOCK ACTIVE 
CLOCK CONTROLLER - FREE RUN
PREF - 1 
SREF - 
AUTO SWREF CLK  ENBL

To force a clock controller to track to the primary clock source (which is probably the PRI on the same card):

.trck pck 0 0              Media Gateway loop and shelf: 0 0
.trck pck 4 0

Remember to reset the loop alarm counters with RCNT <loop> after changing the tracking mode.

Also refer to: UDT E1/T1 - Universal Digital Trunk card

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