UDT E1 T1 clocks
These are built in ld 73, and 60. On Rls 5.0 and above the clocking is a little bit different. Each Media Gateway that has a digital service must have a clock card on it. If the main clock is tied to an E1 then all clocks must be E1 clocks.
Typical Rls 5.0 and above hardware:
- NTDW79 - E1/T1 Universal Digital Trunk (UDT) card;
- NTDW12 - Clock Controller daughterboard.
Place the UDT/PRI/DTI card (with Clock Controller) close to the MGC, preferably in slot one.
Remember, UDT cards must be configured via a TTY first, depending on the circuit configuration.
Define the clock controller parameters:
>LD 73 REQ chg TYPE pri2 Either PRI2/DTI2/JDMI/DDB FOR T1 FEAT syti MGCLK l s c Superloop, shelf, and card of UDT pack with CC daughter board PREF c Card/slot of the PRI2 providing the Primary Reference (in this Media Gateway) SREF c Card/slot for the Secondary reference, if applicable MGCLK Hit <enter> to finish
Clock Controller Maintenance:
A clock controller can operate in one of two modes: tracking and non-tracking (free-run).
Tracking: The clock controller will try and lock to a reference PRI's clock (PREF or SREF, LD 73). If the clock reference is stable, the clock controller will "track" it. There are two stages to clock controller tracking: tracking a reference, and locked onto a reference. The clock controllers should be locked to the reference clock. The secondary reference acts as a backup to the primary reference.
Free-run (non-tracking): The clock controller does not refence any source, but provides its own clock to the system, eg, a Master. Free-run is undesirable if the system is intended to be a slave. If both PREF and SREF are lost, the system will revert to Free-run.
Clock controller comands in LD 60:
- enl cc l s (where l=superloop; s=shelf)
Enable the specified clock controller (loop and shelf).
- dis cc l s (where l=superloop; s=shelf)
Disable the specified clock controller (loop and shelf).
- ssck l s (where l=superloop; s=shelf)
Check status of the specified clock controller (loop and shelf).
- trck aaa l s (Where aaa = PCK, SCLK, or FRUN; l=superloop; s=shelf)
Track MG shelf to the primary or secondary clock reference, or enable free-run (master) mode.
If you experience excessive slips after a PRI outage (DTA103 errors), its very likely that the clock controller has automatically switched to free-run, when it should be tracking. Its good practice to check the clock status after a circuit returns to service.
To check the status of UDT CC daughter board(s), go to LD 60 and enter SSCK:
>LD 60 .ssck 0 0 ENBL CLOCK ACTIVE CLOCK CONTROLLER - LOCKED TO SLOT 1 PREF - 1 SREF - AUTO SWREF CLK - ENBL .ssck 0 1 ENBL CLOCK ACTIVE CLOCK CONTROLLER - FREE RUN PREF - 1 SREF - AUTO SWREF CLK - ENBL .ssck 4 0 ENBL CLOCK ACTIVE CLOCK CONTROLLER - FREE RUN PREF - 2 SREF - AUTO SWREF CLK – ENBL
To force a clock controller to track to the primary clock source:
.trck pck 0 0 Media Gateway loop and shelf: 0 0 .trck pck 0 1 .trck pck 4 0
Also refer to: UDT E1/T1 - Universal Digital Trunk card